Compact Clock Skew Scheme for FPGA based Wave- Pipelined Circuits

FPGAs have advantage over ASICs such as rapid prototyping, in circuit programmability, lower NRE costs and results in more economical designs. In conventional pipelining technique, the operating frequency is increased by dividing the combinational logic into number of stages and registers are introduced between the stages. All the registers are fed with a global clock. This improves the speed of the system but at the cost of increased number of registers, area, latency, power and clock routing complexity Wave-pipelining technique is an approach which improves the speed of the circuit with less area and clock loads. A compact clock skew scheme is proposed in this paper to improve the performance of the wave pipelined circuits. The proposed technique is evaluated by implementing 4 tap FIR filters using Distributed Arithmetic Algorithm (DAA) by using 3 different schemes: non-pipelining, pipelining and wave pipelining on XILINX platform. The power, area and latency comparison between the 3 different schemes are shown. It is found that wave pipelining is best when compared to area and power .